- Shifters
- Hard-Wired Shifter
- Programmable shifter
- Barrel Shifter
- Logarithmic shifter
- Adder
- Full Adder
- Complementary Static CMOS Full Adder Cell
- Ripple Carry Adder
- Transmission-Gate-Based Adder
- Manchester Carry Gates
- Carry-Bypass Adder
- Manchester Carry-Bypass Adder
- Carry-Select Adder
- Carry-Look-Ahead Adder
- Multiplier
- Array Multiplier
- Carry-Save Multiplier
- CSA Trees
- Baugh-Wooley Array Multiplier
- Low Power
- Parallel Functional Blocks
- Pipeline Structure of functional blocks
- Multiple supply voltages
- Dynamic voltage and frequency scaling (DVFS)
- Power-down mode
- Clock gating
- Power gating
- Design Entry Tool
- Simulation (6) + Analysis (1)
- Circuit Simulation (Transistor Level Simulation)
- Switch Level Simulation
- Gate Level Simulation (Logic Simulation)
- Timing Simulation
- Static Timing Analysis
- Entry Delay
- Stage Delay
- Exit Delay
- Functional Simulation
- Represents the intended hardware structure
- Behavioural Simulation
- Describes only the input-output functionality
- Design Verification
- Electrical Verification
- Timing Verification
- Formal Verification
- Implementation Approaches
- Semi-Custom IC
- Gate Array
- Standard Cell
- Programmable Logic Device
- PAL, PLA, PROM, ROM
- CPLD
- FPGA
- Full-Custom IC
- Design Synthesis
- Circuit Synthesis
- Derivation of transistor netlist from the logic equations
- Transistor Sizing to meet performance constraints
- Logic Synthesis
- Logic minimization
- Technology mapping
- Combinational Logic Synthesis
- Sequential Logic Synthesis
- State Minimization
- State Encoding
- State Machine Decomposition
- Retiming
- Architecture Synthesis (High-Level)
- Operation Scheduling
- Data Path Allocation
- Register Allocation
- Module Allocation
- Interconnect Allocation
- Testing
- Diagnostic test
- Functional test
- Parametric test
- Fault Models
- Short-circuits between signals
- Short-circuits between supply rails
- Floating nodes
- Stuck-At Module