EE6306 240916 quiz 1 A

Qa.

Build the same logic circuit use the compulmentary CMOS transister. Assume that the ratio of PMOS to the NMOS of inverter is , give all the ratio of transistor in the circuit you build.

Qb.

(1) Use the dynamic circuit and DCVSL to build the NOR gate. Write the advantages and disadvantages of them compared with the complementary CMOS. (2) Assume there are four logic components with working time of , , and . If use a four stage pipline to build it, what is the througput and the system clock frequency. How to improve without add overhead?

Qc.

(1) Use the PTL to build an AND gate and a 4-input MUX. (2) Due to the circuit structure of PTL circuit, the output voltage will be degraded along the time. Write out the way to fully regrade it without using the transmission gate.