1. List 3 methods for IC design verification. 2. List 3 methods for optimizing the synthesis of sequential logic circuits. 3. List 2 methods for data path allocation. 4. Provide a test vector for SA0 (Stuck-at-0) using the D algorithm for a Z node. 5. List 3 methods to reducing the delay of carry chain in adders. 6. List 3 low-power design techniques.
